Open AccessDelay Comparison for 16x16 Vedic Multiplier Using RCA and CLA
Author(s) -
M. Bhavani,
Mahendra Kumar,
K. R. Rao
Publication year - 2016
Publication title -
international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.277
H-Index - 22
ISSN - 2088-8708
DOI - 10.11591/ijece.v6i3.pp1205-1212
Subject(s) - adder , verilog , multiplier (economics) , arithmetic , carry save adder , computer science , booth's multiplication algorithm , serial binary adder , computer hardware , parallel computing , mathematics , field programmable gate array , telecommunications , economics , macroeconomics , latency (audio)
In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.