Open AccessInfluence of Gate Material and Process on Junctionless FET Subthreshold Performance
Author(s) -
Munawar Agus Riyadi,
Irawan D Sukawati,
Teguh Prakoso,
Darjat Darjat
Publication year - 2016
Publication title -
international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.277
H-Index - 22
ISSN - 2088-8708
DOI - 10.11591/ijece.v6i2.pp895-900
Subject(s) - subthreshold conduction , scaling , process (computing) , subthreshold slope , materials science , silicon on insulator , computer science , optoelectronics , doping , mosfet , nanotechnology , electrical engineering , engineering physics , electronic engineering , transistor , silicon , voltage , physics , engineering , mathematics , geometry , operating system
The recent progress of dimension scaling of electronic device into nano scale has motivated the invention of alternative materials and structures. One new device that shows great potential to prolong the scaling is junctionless FET (JLFET). In contrast to conventional MOSFETs, JLFET does not require steep junction for source and drain. The device processing directly influence the performance, therefore it is crucial to understand the role of gate processing in JLFET. This paper investigates the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process techniques. The result shows that in terms of subthreshold slope, JLFET approaches near ideal value of 60 mV/decade, which is superior than the SOI FET for similar doping rate. On the other hand, the threshold value shows different tendencies between those types of device.