Open AccessField-programmable gate array design of image encryption and decryption using Chua’s chaotic masking
Author(s) -
Wisal Adnan Al-Musawi,
Wasan A. Wali,
Mohammed A. Al-Ibadi
Publication year - 2022
Publication title -
international journal of power electronics and drive systems/international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
eISSN - 2722-2578
pISSN - 2722-256X
DOI - 10.11591/ijece.v12i3.pp2414-2424
Subject(s) - field programmable gate array , computer science , encryption , synchronization (alternating current) , gate array , computer hardware , chaotic , shift register , microprocessor , cryptography , key (lock) , distortion (music) , embedded system , algorithm , chip , artificial intelligence , telecommunications , amplifier , channel (broadcasting) , computer security , operating system , bandwidth (computing)
This article presents a simple and efficient masking technique based on Chua chaotic system synchronization. It includes feeding the masked signal back to the master system and using it to drive the slave system for synchronization purposes. The proposed system is implemented in a field programmable gate array (FPGA) device using the Xilinx system generator tool. To achieve synchronization, the Pecora-Carroll identical cascading synchronization approach was used. The transmitted signal should be mixed or masked with a chaotic carrier and can be processed by the receiver without any distortion or loss. For different images, the security analysis is performed using the histogram, correlation coefficient, and entropy. In addition, FPGA hardware co-simulation based Xilinx Artix7 xc7a100t-1csg324 was used to check the reality of the encryption and decryption of the images.