Open AccessHigh-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications
Author(s) -
Paolo Visconti,
Ramiro Velázquez,
Stefano Capoccia,
Roberto De Fazio
Publication year - 2021
Publication title -
international journal of power electronics and drive systems/international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
eISSN - 2722-2578
pISSN - 2722-256X
DOI - 10.11591/ijece.v11i5.pp4221-4232
Subject(s) - encryption , computer science , field programmable gate array , synchronization (alternating current) , embedded system , interoperability , encryption software , orthogonal frequency division multiplexing , computer hardware , network packet , throughput , gigabit , cryptography , algorithm , wireless , multiple encryption , computer network , disk encryption , operating system , telecommunications , channel (broadcasting)
In this research work, a fast and lightweight AES-128 cypher based on the Xilinx ZCU102 FPGA board is presented, suitable for 5G communications. In particular, both encryption and decryption algorithms have been developed using a pipelined approach, so enabling the simultaneous processing of the rounds on multiple data packets at each clock cycle. Both the encryption and decryption systems support an operative frequency up to 220 MHz, reaching 28.16 Gbit/s maximum data throughput; besides, the encryption and decryption phases last both only ten clock periods. To guarantee the interoperability of the developed encryption/decryption system with the other sections of the 5G communication apparatus, synchronization and control signals have been integrated. The encryption system uses only 1631 CLBs, whereas the decryption one only 3464 CLBs, ascribable, mainly, to the Inverse Mix Columns step. The developed cypher shows higher efficiency (8.63 Mbps/slice) than similar solutions present in literature.