Open AccessAnalysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials
Author(s) -
Hyun–Kyo Jung,
Byungon Kim
Publication year - 2021
Publication title -
international journal of power electronics and drive systems/international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
eISSN - 2722-2578
pISSN - 2722-256X
DOI - 10.11591/ijece.v11i5.pp3882-3889
Subject(s) - dielectric , materials science , mosfet , gate oxide , threshold voltage , gate dielectric , current ratio , analytical chemistry (journal) , optoelectronics , electrical engineering , voltage , transistor , chemistry , finance , chromatography , market liquidity , economics , engineering
The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO 2 /high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 10 4 or less is shown for SiO 2 , but the on-off current ratio for TiO 2 ( k =80) increases to 10 7 or more.