Open AccessCompressor based approximate multiplier architectures for media processing applications
Author(s) -
Uppugunduru Anil Kumar,
Syed Ershad Ahmed
Publication year - 2021
Publication title -
international journal of power electronics and drive systems/international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
eISSN - 2722-2578
pISSN - 2722-256X
DOI - 10.11591/ijece.v11i4.pp2953-2961
Subject(s) - multiplier (economics) , computer science , gas compressor , computation , adder , error detection and correction , algorithm , computer hardware , arithmetic , mathematics , telecommunications , engineering , mechanical engineering , economics , macroeconomics , latency (audio)
Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.