Open AccessTask mapping and routing optimization for hard real-time Networks-on-Chip
Author(s) -
M. Norazizi Sham Mohd Sayuti,
Farida Ridzuan,
Zul Hilmi Abdullah
Publication year - 2019
Publication title -
bulletin of electrical engineering and informatics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 12
ISSN - 2302-9285
DOI - 10.11591/eei.v8i2.1395
Subject(s) - heuristics , computer science , distributed computing , routing (electronic design automation) , task (project management) , execution time , computation , network on a chip , function (biology) , design space exploration , population , embedded system , engineering , algorithm , systems engineering , operating system , demography , evolutionary biology , sociology , biology
Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.