Open AccessProcess Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer
Author(s) -
Laura Žurauskaitė,
PerErik Hellström,
Mikael Östling
Publication year - 2020
Publication title -
ecs journal of solid state science and technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.488
H-Index - 51
eISSN - 2162-8777
pISSN - 2162-8769
DOI - 10.1149/2162-8777/abd48c
Subject(s) - passivation , materials science , epitaxy , oxide , desorption , stack (abstract data type) , monolayer , optoelectronics , layer (electronics) , hydrogen , analytical chemistry (journal) , nanotechnology , chemistry , metallurgy , adsorption , computer science , organic chemistry , chromatography , programming language
In this work we study the epitaxial Si growth with Si 2 H 6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 °C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D it < 5·10 11 cm −2 eV −1 . Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm 2 O 3 /HfO 2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 3·10 11 eV −1 cm −2 and a significant improvement in oxide trap density compared to GeO x passivation.