Mixed Microprocessor‐Random Logic Approach for Innovative Pacing Systems

Modern pacing systems are becoming more and more sophisticated. Conversion of the information supplied by a sensor into suitable parameters for a rate controlling algorithm and the management of complex timing are common tasks for an integrated circuit (IC) in cardiac pacing. An effective solution consists of using a microprocessor to implement algorithms and pacing modes in a flexible way. The key point of using the same hardware resources for different tasks on a time sharing basis allows the design of a less complex 1C when compared to a random logic structure with the same performances. The major design problems in a full microprocessor solution are its relatively low operating speed due to the low frequency clock necessary for low current drain, and the sequential structure of the machine itself. This can lead to unacceptable timing inaccuracy in all situations requiring the management of complex decision trees. In order to take full benefit from the advantages of a microprocessor structure without these drawbacks, a mixed microprocessor‐random logic approach has been investigated. This architecture uses a microprocessor core to perform all high level nonreal‐time operations (setup of the pacing cycle, data reduction and processing, data integrity checks) while a set of random logic peripherals is used for all critical timing aspects.