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Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration
Author(s) -
Weng C.J.
Publication year - 2009
Publication title -
strain
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.477
H-Index - 47
eISSN - 1475-1305
pISSN - 0039-2103
DOI - 10.1111/j.1475-1305.2009.00599.x
Subject(s) - copper interconnect , design for manufacturability , semiconductor device fabrication , wafer , process integration , materials science , semiconductor , lithography , process (computing) , semiconductor device , dual (grammatical number) , electronic engineering , optoelectronics , computer science , mechanical engineering , nanotechnology , engineering , process engineering , art , literature , layer (electronics) , dielectric , operating system
Abstract: The performance of the manufacturing process in each of these areas determines the overall manufacturability of the process. As device geometries are reduced, understanding and minimising the sources of process‐induced defects is critical to achieving and maintaining high device yields. This paper presents a comprehensive investigation of a novel metrology on semiconductor process module integration and technology on optimal integrated lithography processes and solution to the problem of defects reduction on semiconductor wafer in sub‐micron processes integration. As dual damascene integration copper process is complicated and critical in semiconductor processes. It has been common knowledge that pattern collapse and missing of this process and numerous defects could be prevented by optimal the process module tuning. To investigate novel semiconductor process integration on deep pattern aspect ratio effects of sub‐micron semiconductor wafer BEOL (Back‐End‐Of‐Line) structure were included in this study. Moreover, the electrical device investigations of device checking were also included.