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Statistical Determination of Plating Process Variables for Multilayer Ceramic Chip Capacitors
Author(s) -
Benm Doug A.,
Feltz Carol J.,
Haynes Richard,
Pinault Steven C.
Publication year - 1989
Publication title -
journal of the american ceramic society
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.9
H-Index - 196
eISSN - 1551-2916
pISSN - 0002-7820
DOI - 10.1111/j.1151-2916.1989.tb06074.x
Subject(s) - plating (geology) , materials science , capacitor , solderability , ceramic capacitor , composite material , capacitance , metallurgy , voltage , layer (electronics) , electrical engineering , chemistry , engineering , electrode , geophysics , geology
The effects of the following barrier layer plating process variables on reliability of multilayer ceramic chip capacitors are discussed: media type, nickel plating thickness, lead concentration, pH, tin plating current density, number of capacitors, and percent loading of the plating barrel. The dielectric was formulated from a lead magnesium niobate material. Evaluations were done with respect to capacitance, dissipation factor, conductance, dry life (temperature bias) test, solderability (with and without steam aging), and voltage surge test. Several of the in‐process variables studied were found to have a statistically significant effect on some of these response variables. The data indicate that the most significant inprocess parameters in the barrier layer process, of those included in this study, are media type and percentage loading of the barrel. Variables of marginal significance are number of capacitors, lead in the bath, and tin plating current density. The other variables had no discernible effect on the response variables studied. The presence of such a large experimental error in life test was a significant outcome of the study and indicates a need for further study on means of obtaining reproducible life‐test results after plating.