1.0 Introduction

This paper investigates the performance differences between a non-adaptive and an adaptive processor interconnect switch. We have designed and implemented two 5x5 full duplex switches, one that performs non-adaptive routing, and one that performs adaptive routing in the Verilog hardware description language. We connected these switches up into a 16-node 4x4 network that could be configured as either a mesh topology or a torus topology (Shown in Figure 1). We then evaluated the performance of the switches using VERA, a C/C++ style language that can interface into Verilog code. Using VERA allowed us to perform numerous complex test cases to thoroughly evaluate and validate our network of switches.