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Optimization of TSV interconnects and BEOL layers under annealing process through fracture evaluation
Author(s) -
Qin F.,
Zhang M.,
Dai Y.,
Chen P.,
An T.,
He H.,
Zhang H.,
Zheng J.
Publication year - 2020
Publication title -
fatigue and fracture of engineering materials and structures
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.887
H-Index - 84
eISSN - 1460-2695
pISSN - 8756-758X
DOI - 10.1111/ffe.13206
Subject(s) - materials science , through silicon via , interconnection , composite material , annealing (glass) , back end of line , dielectric , thermal expansion , optoelectronics , electronic engineering , wafer , computer science , engineering , computer network
Through silicon via (TSV) is a crucial interconnection structure in 3‐D integrated circuits. However, protrusion and intrusion of TSV‐Cu caused by annealing could lead to cracking and failure of back‐end‐of‐line (BEOL) layers and TSV interconnects due to mismatch of coefficient of thermal expansion. In this paper, optimizations of TSV interconnects and BEOL layers under annealing process are investigated based on fracture evaluation. Influences of geometrical factors including the TSV geometry dimension, the distance between TSV and BEOL layers, and pitch size of Cu via on energy release rate and J ‐integral are studied for TSV interconnects and BEOL layers with cracks. Effect of material properties for low k dielectrics on interfacial fracture of BEOL layers and TSV interconnects is also given. Optimized geometrical factors and optimized material properties of low k dielectrics are presented in this paper. Fracture‐based method sheds a light on emerging electronic packaging optimization.