Open AccessA 1.15-ps Bin Size and 3.5-ps Single-Shot Precision Time-to-Digital Converter With On-Board Offset Correction in an FPGA
Author(s) -
X. Qin,
L. Wang,
D. Liu,
Y. Zhao,
X. Rong,
J. Du
Publication year - 2017
Publication title -
ieee transactions on nuclear science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.537
H-Index - 122
eISSN - 1558-1578
pISSN - 0018-9499
DOI - 10.1109/tns.2017.2768082
Subject(s) - nuclear engineering , bioengineering
This paper presents the implementation of a high-resolution time-to-digital converter (TDC), which is adapted to varying environmental conditions. The TDC is implemented in field-programmable gate arrays (FPGA), using carry chains to achieve fine time measurement. Multiple carry chains are integrated in a single TDC channel for resolution enhancement. The TDC performance would suffer greatly without temperature compensation due to its sensitivity to the operating temperature. In order to improve the TDC adaptability, we analyzed the temperature-dependent delay variation function, and designed a powerful offset canceler to ensure stable performance of our TDC over a wide temperature range. The offset canceler can effectively correct the delay offset over temperature for the carry chain as well as for the signal transmission path. The TDC channels are tested to be fully functional with the operating temperature continuously varying from −20 °C to 60 °C. The averaged TDC bin size is 1.15 ps, and the single-shot precision is 3.5 ps. The duplications of the TDCs in three FPGA chips show good performance reproducibility according to the tests in a temperature chamber.