32k Channel Readout IC for Single Photon Counting Pixel Detectors with ${75}\ \mu\hbox{m}$ Pitch, Dead Time of 85 ns, ${9}\ {{\rm e}^ - }\ \hbox{rms}$ Offset Spread and 2% rms Gain Spread

This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm × 20.15 mm. The core of the IC is a matrix of 128 × 256 square-shaped pixels of 75 μm pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bumpbonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to 123 e^- rms (for the peaking time of 40 ns) and each pixel dissipates 26 μW. Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only 9 e^- rms with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.