Metallic Single Electron Transistors: Impact of Parasitic Capacitances on Small Circuits

A method of simulating metallic-island single electron transistors (SETs) and small circuits which speeds up the design-fabrication-characterization cycle is proposed. The method combines finite-elements method to extract device capacitance matrix and standard master equations solved by Monte Carlo to simulate device transport characteristics based on the fabrication geometry and materials. It allows simulation of SET circuits. The simulation method is detailed using two capacitively coupled SETs acting either as an electron box or a sensor. The method is also compared with isolated SETs fabricated using the nanodamascene process and characterized at low temperatures. Experimental devices show clear Coulomb blockade diamonds at 1.5 K and charging energies up to 3 meV. The simulation platform predicts the electrical behavior accurately with minimal fitting parameters. This method allows rapid and accurate design iterations before costly fabrication.