Open AccessHigh-R Poly Resistance Deviation Improvement From Suppressions of Back-End Mechanical Stresses
Author(s) -
Tingyou Lin,
Yingchieh Ho,
Chauchin Su
Publication year - 2017
Publication title -
ieee transactions on electron devices
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.828
H-Index - 186
eISSN - 1557-9646
pISSN - 0018-9383
DOI - 10.1109/ted.2017.2742702
Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas
This paper investigates techniques for N-type high-resistance polysilicon resistors to reduce the resistance deviation which is caused by the back-end mechanical stress. In the back-end layers of the wafer, a top metal thickness equal to 3 μm is provided to increase the heat allowing current density in the metal routes of power ICs. The top metal processing yields the mechanical stress to increase the resistance by the piezoresistance effect. To eliminate the mechanical stresses, a new layout is proposed with the full passivation cutting (FPC). The resistor with an FPC uses the passivation film separation to create a physical empty room for suppressing the mechanical stresses on the polysilicon. The proposed layout has been verified in the 0.4-μm bipolar-CMOS-DMOS process, and the resistance shifts were compared with other four-type layouts. Compared to those original layouts, the proposed layout exhibits the improvements in the resistance deviation reduction in the maximum ratio 20.80%.