Open AccessWafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
Author(s) -
S. Y. Hou,
W. Chris Chen,
Clark Hu,
Christine Chiu,
K. C. Ting,
T. S. Lin,
W. H. Wei,
W. C. Chiou,
Vic J. C. Lin,
Victor C. Y. Chang,
C. T. Wang,
C. H. Wu,
Douglas Yu
Publication year - 2017
Publication title -
ieee transactions on electron devices
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.828
H-Index - 186
eISSN - 1557-9646
pISSN - 0018-9383
DOI - 10.1109/ted.2017.2737644
Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas
State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.