Fast Online Diagnosis and Recovery of Reconfigurable Logic Fabrics Using Design Disjunction

Design disjunction is developed to offer a broad coverage, high resolution, and low overhead approach to online diagnosis and recovery of reconfigurable fabrics. Design disjunction leverages the condensed diagnosability of $T$ logic resources to achieve self-recovery using partial reconfiguration in O(log $T$ ) steps. Reconfiguration is guided by the constructive property of $f$ -disjunctness which forms O(log $T$ ) resource groups at design-time. Resolution of $f$ simultaneous resource faults is shown to be guaranteed when the resource groups are mutually $f$ -disjunct. This extends run-time fault resilience to a large resource space with certainty for up to $f$ faults using a decision-free resolution process that also provides a high likelihood of identifying the fault’s location to a fine granularity. Finally, design disjunction is parameterized to accommodate the low coverage issue of functional testing for which inarticulate tests can otherwise impair fault isolation. Experimental results for MCNC and ISCAS benchmarks on a Xilinx 7-series field programmable gate array (FPGA) demonstrate $f$ -diagnosability at the individual slice level with a minimum average isolation accuracy of $96.4$  percent ( $94.4$ percent) for $f=1$  ( $f=2$ ). Results have also demonstrated millisecond order recovery with a minimum increase of $83.6$ percent in fault coverage compared to $N$ -modular redundancy (NMR) schemes. Recovery is achieved while incurring an average critical path delay impact of only $1.49$ percent and energy cost roughly comparable to conventional two-MR approaches.