Open AccessA Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits
Author(s) -
Soheil Nazar Shahsavani,
Massoud Pedram
Publication year - 2019
Publication title -
ieee transactions on applied superconductivity
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.467
H-Index - 84
eISSN - 1558-2515
pISSN - 1051-8223
DOI - 10.1109/tasc.2019.2943930
Subject(s) - clock skew , digital clock manager , clock gating , clock domain crossing , skew , computer science , cpu multiplier , algorithm , synchronous circuit , static timing analysis , clock signal , parallel computing , topology (electrical circuits) , mathematics , embedded system , telecommunications , combinatorics , jitter
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