An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC | Zendy

Hegong Wei | Zendy; Chi-Hang Chan | Zendy; U-Fat Chio | Zendy; Sai-Weng Sin | Zendy; Seng-Pan U | Zendy; Rui Paulo Martins | Zendy; Franco Maloberti | Zendy

AI Assistant Blog Pricing

Home ZAIA Blog

Open Access

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

Author(s) -

Hegong Wei,

Chi-Hang Chan,

U-Fat Chio,

Sai-Weng Sin,

Seng-Pan U,

Rui Paulo Martins,

Franco Maloberti

Publication year - 2012

Publication title -

ieee journal of solid-state circuits

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 2.571

H-Index - 215

eISSN - 1558-173X

pISSN - 0018-9200

DOI - 10.1109/jssc.2012.2214181

Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas , computing and processing

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm².

The content you want is available to Zendy users.

Already have an account? Click here to sign in.

Having issues? You can contact us here

Accelerating Research