Open AccessA 25-Gb/s 5 × 5 mm2 Chip-Scale Silicon-Photonic Receiver Integrated With 28-nm CMOS Transimpedance Amplifier
Author(s) -
Daisuke Okamoto,
Yasuyuki Suzuki,
Kenichiro Yashiki,
Yasuhiko Hagihara,
Masatoshi Tokushima,
Junichi Fujikata,
Mitsuru Kurihara,
Junichi Tsuchida,
Takaaki Nedachi,
Jun Inasaka,
Kazuhiko Kurata
Publication year - 2016
Publication title -
journal of lightwave technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.346
H-Index - 200
eISSN - 1558-2213
pISSN - 0733-8724
DOI - 10.1109/jlt.2015.2500365
Subject(s) - communication, networking and broadcast technologies , photonics and electrooptics
We have developed a 5 × 5 mm2 compact silicon-photonic receiver with a 28-nm CMOS transimpedance-amplifier (TIA) chip. The receiver chip was designed using a photonics—electronics convergence design technique for the realization of high-speed and high-efficiency operation because the interfaces of the optical and electrical components greatly influence the receiver characteristics. Optical pins were used to obtain easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA enhanced the 3-dB bandwidth because its characteristic impedance is greater than the TIA input impedance. Coplanar waveguides (CPWs) on the etched SOI wafer achieved a low insertion loss because the overlap between the electric fields of the CPWs and the silicon layer was reduced. We demonstrated 25-Gb/s error-free operation at both 25 and at 85 °C. The minimum sensitivities and power consumptions of the receivers were −11.0 dBm and 2.3 mW/Gb/s at 25 °C and −10.2 dBm and 2.5 mW/Gb/s at 85 °C, respectively. These results show that our receiver can be applied for practical use at high temperatures.