Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout | Zendy

Eisuke Anju | Zendy; Iriya Muneta | Zendy; Kuniyuki Kakushima | Zendy; Kazuo Tsutsui | Zendy; Hitoshi Wakabayashi | Zendy

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Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout

Author(s) -

Eisuke Anju,

Iriya Muneta,

Kuniyuki Kakushima,

Kazuo Tsutsui,

Hitoshi Wakabayashi

Publication year - 2018

Publication title -

ieee journal of the electron devices society

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.69

H-Index - 31

ISSN - 2168-6734

DOI - 10.1109/jeds.2018.2882406

Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas

In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure. This is attributed to an increase in heat dissipation mainly from heat source to bulk wafer. Moreover, we proposed the p/n-stacked nanowire on bulk FinFET and its 6T-SRAM layout. Area of the proposed SRAM was reduced approximately 15%, as compared to the conventional cell layout.

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