Open Access3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
Author(s) -
Wen-Wei Shen,
Yu-Min Lin,
Shang-Chun Chen,
Hsiang-Hung Chang,
Tao-Chih Chang,
Wei-Chung Lo,
Chien-Chung Lin,
Yung-Fa Chou,
Ding-Ming Kwai,
Ming-Jer Kao,
Kuan-Neng Chen
Publication year - 2018
Publication title -
ieee journal of the electron devices society
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.69
H-Index - 31
ISSN - 2168-6734
DOI - 10.1109/jeds.2018.2815344
Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-μm-diameter/50-μm-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-μm diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.