Open AccessGAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node
Author(s) -
Ya-Chi Huang,
Meng-Hsueh Chiang,
Shui-Jinn Wang,
Jerry G. Fossum
Publication year - 2017
Publication title -
ieee journal of the electron devices society
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.69
H-Index - 31
ISSN - 2168-6734
DOI - 10.1109/jeds.2017.2689738
Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas
Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.