Open AccessV-Shaped InAs/Al0.5Ga0.5Sb Vertical Tunnel FET on GaAs (001) Substrate With I $_{\text {ON}}=\text {433}\,\,\mu$ A. $\mu$ m $^{-\text {1}}$ at V $_{\text {DS}}= \text {0.5}$ V
Author(s) -
Vinay Kumar Chinni,
Mohammed Zaknoune,
Christophe Coi,
Laurence Morgenroth,
David Troadec,
Xavier Wallart,
Ludovic Desplanque
Publication year - 2016
Publication title -
ieee journal of the electron devices society
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.69
H-Index - 31
ISSN - 2168-6734
DOI - 10.1109/jeds.2016.2630499
Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas
We report on the fabrication of a near broken InAs/Al0.5Ga0.5Sb vertical TUNNEL field effect transistor (TFET). The epitaxial structure is grown on a GaAs (001) substrate thanks to large mismatch accommodation at the GaSb/GaAs interface. The fabrication process involves an anisotropic and selective wet chemical etching of the InAs channel to form a V-shaped mesa with lateral side gates. This new architecture provides a large ON-current at room temperature while enabling an efficient pinch-off thanks to a reduced body thickness near the tunneling interface. With low temperature measurements, we identify the different mechanisms limiting the subthreshold slope at room temperature. At 77 K, where the impact of defects is reduced, a minimum subthreshold slope of 71 mV/decade is achieved for VDS = 0.1 V with an ION/IOFF current ratio larger than 6 decades demonstrating that a good trade-off between ON current and switching efficiency could be obtained with a near broken gap heterostructure based n-TFET.