High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates

We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high- $\kappa $ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing ${S}$ is 76.8 mV/dec., and the peak transconductance ${g} _{\mathrm{ m}}$ is 1.65 mS/ ${\mu }\text{m}$ , at ${V} _{\mathrm{ ds}}$ of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length ${L} _{\mathrm{ g}}$ of 90 nm, a nanowire height ${H} _{\mathrm{ NW}}$ of 25 nm, and a nanowire width ${W} _{\mathrm{ NW}}$ of 20 nm, resulting in ${Q}~\equiv ~{g} _{\mathrm{ m}}/{S} \,\, = \,\, 21.5$ , a record for InAs on silicon. Furthermore, we report a source/drain resistance ${R} _{\mathrm{ sd}}$ of 160– $200~\Omega \cdot {\mu }\text{m}$ , amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity ${v} _{\mathrm{ tx}}$ of 3– $4\times 10^{7}$ cm/s and back-scattering coefficient ${r} _{\mathrm{ c}}$ as a function of gate length.