Open AccessOn-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology
Author(s) -
Po-Yen Lin,
Yu-Lun Chiu,
Yuh-Te Sung,
Jim Chen,
Tzong-Sheng Chang,
Ya-Chin King,
Chrong Jung Lin
Publication year - 2015
Publication title -
ieee journal of the electron devices society
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.69
H-Index - 31
ISSN - 2168-6734
DOI - 10.1109/jeds.2015.2475257
Subject(s) - components, circuits, devices and systems , engineered materials, dielectrics and plasmas
A new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell. Merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process. The scaled gate length enables the SAN cell be erased by band-to-band hot hole. For multiple-time-programming operation, two effective recovery methods are proposed to recover on/off window after cycling stress. Both ac and dc methods are applied to eliminate deep-trapped charges via electrical self-heating. Experimental data demonstrates dc recovery methods that provide nearly full damage anneal capability and, in turn, effectively extend SAN cell's endurance level.