Open AccessCombining Relaxation With NCL_X For Enhanced Optimization Of Asynchronous Null Convention Logic Circuits
Author(s) -
Danylo Khodosevych,
Alexander C. Bodoh,
Ashiq A. Sakib,
Scott C. Smith
Publication year - 2023
Publication title -
ieee access
Language(s) - English
Resource type - Journals
ISSN - 2169-3536
DOI - 10.1109/access.2023.3318132
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
Quasi-Delay Insensitive (QDI) asynchronous circuits, such as NULL Convention Logic (NCL), are being utilized more and more in industry to mitigate timing issues associated with process, voltage, and temperature (PVT) variations, which are making timing closure for synchronous circuits more problematic as transistor feature size continues to shrink. This paper combines aspects of relaxation optimization with utilizing the NCL_X architecture for select portions of the circuit, resulting in an integrated optimization method for NCL circuits that achieves an average speedup of 6.8% to 12.5%, using on average 24.6% fewer to 3.7% more transistors, compared to existing NCL synthesis and optimization methods.