Open AccessAutomatic PCB Layout Optimization of a DC-DC Converter Through Genetic Algorithm Regarding EMC Constraints
Author(s) -
Wided Belloumi,
Arnaud Breard,
Omssad Hajji,
Christian Vollaire,
Jaleleddine Ben Hadj Slama
Publication year - 2021
Publication title -
ieee access
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.587
H-Index - 127
ISSN - 2169-3536
DOI - 10.1109/access.2021.3124935
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
This paper proposes an optimization approach for an automatic buck converter printed circuit board (PCB) design regarding the electromagnetic compatibility (EMC) constraints. The proposed solution is based on the combination of a genetic algorithm (GA) and a Dijkstra algorithm to generate the different PCB layout designs. Afterwards, a numerical modeling approach, taking into account all the stray elements, is proposed to obtain an accurate equivalent circuit for the PCB layout using ANSYS Q3D software. Subsequently, the complete behavior of the converter is simulated within SIMPLORER, including the electrical models of the components, the Line Impedance Stabilization Network (LISN) module as well as the PCB layout model. This aims to compute the conducted disturbances such as the common and the differential mode voltages. Then, this approach is implemented in an optimized process to reach the optimal geometry for the printed circuit board layout with the lowest parasitic effect to fit the EMC requirements. Finally, measurements are performed, and the optimization results are presented and investigated, in comparison with reference PCB layout to assess the efficiency of the proposed methodology.