Open AccessOptimizing PWM Control for Efficiency and Reduction of False Turn-On Events in Synchronous Buck GaN Converters
Author(s) -
Nishant Kashyap,
Jennifer Bauman
Publication year - 2021
Publication title -
ieee access
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.587
H-Index - 127
ISSN - 2169-3536
DOI - 10.1109/access.2021.3121633
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
Half-bridge GaN power converters are susceptible to false turn-on events, which can lead to shoot-through and potentially device-damaging currents. There are three main parameters that can be adjusted in PWM schemes to reduce the likelihood of false turn-on events: negative gate bias, gate resistance, and deadtime. However, these PWM parameters also affect converter efficiency in the inverse way, meaning less false turn-on events must be balanced with lowered efficiency. The novelty of this paper is to investigate the trade-off between reducing GaN false turn-on events (by reducing the transient peak of gate to source voltage) and maximizing the power converter efficiency, which has not been done in prior work. This paper investigates this trade-off using a synchronous buck converter over numerous operating points with variation of the three key PWM parameters. Six converter scenarios are considered with input voltage of 200/400V, switching frequency of 50/100kHz, and output power of 500W/1kW. For each scenario, negative gate bias is set to ™4.4V and −5V, gate on-resistance is set to $10\Omega $ and $12.5\Omega $ , and deadtime is varied at 60ns, 80ns, and 110ns. The results are organized into Pareto plots to find optimal points for efficiency and reduction of false turn-on events. The experimental results show that a further negative gate bias (−5V) most significantly reduces the false turn-on voltage peak and still achieves very high efficiency with appropriate selection of gate resistance and deadtime.