Assessing the Performance of Analog Training for Transfer Learning

Analog in-memory computing is a next-generation computing paradigm that promises fast, parallel, and energy-efficient deep learning training and transfer learning (TL). However, achieving this promise has remained elusive due to the lack of suitable training algorithms. Analog memory devices exhibit asymmetric and nonlinear switching behavior in addition to device-to-device variation, meaning that most, if not all, of the current off-the-shelf training algorithms cannot achieve good training outcomes. Recently introduced algorithms have attracted limited attention, as they require bi-directionally switching devices of unrealistically high symmetry and precision and are highly sensitive. A new algorithm, chopped TTv2 (c-TTv2), has been introduced, which leverages the chopped technique to address many of these challenges. In this brief, we evaluate the accuracy and the performance of the c-TTv2 algorithm for analog TL using ResNet and Swin-ViT models, pre-trained on the CIFAR10 dataset, on a fine-tuning task using two subsets of the CIFAR100 dataset. We also investigate the robustness of our algorithm to changes in some device and circuit non-idealities, including weight transfer noise, write noise, symmetry point skew, symmetry point variability, pulse update noise, mean pulse response, device-to-device variability, the number of states, output noise, I/O resolution, and the minimum and maximum conductance device-to-device variability. We demonstrate that the c-TTv2 algorithm mostly surpasses the performance of analog/digital training and narrows the performance gap between analog and digital TL while being robust to changes in device and circuit non-idealities.