Halfbex: RISC-V Narrow Data Path Optimization for Energy Reduction

This brief explores narrow data path optimizations for energy-efficient processing. A 32-bit RISC-V processor implementing the RV32IC instruction set is proposed. The core’s data path width is reduced to 16 bits to save power and silicon area. Although this requires multi-cycle instruction execution, introduced targeted optimizations leverage instruction semantics and data characteristics to eliminate many redundant cycles. Thereby, the throughput can often be maintained. Extensive benchmarking confirms the effectiveness of the approach. Post-layout simulation of the placed-and-routed design showcases system-wide energy savings between 3% and 35% compared to the Ibex processor.