Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing

This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input multi-output (MIMO) systems. SRAM-based IMCs are the state-of-the-art for executing deep learning workloads in terms of energy efficiency and compute density. However, given the more stringent accuracy requirements of massive MIMO signal detection compared to deep learning, it remains an open question whether the energy efficiency benefits of IMCs can be preserved while meeting these accuracy requirements. This paper systematically explores the energy-accuracy trade-off in massive MIMO signal detectors designed using SRAM-based IMCs. Through transistor-level behavioral modeling and simulations in 28 nm CMOS process, we evaluate the energy per information bit ( $E_{\mathrm {b}}$ ), error vector magnitude (EVM) and symbol error rate (SER) of linear detectors designed using SRAM-based IMCs for various wireless channels. We perform extensive design space exploration to determine the design parameters and operating conditions under which IMC-based linear detectors achieve significantly better energy efficiency than conventional digital implementations, while maintaining comparable accuracy. Our results show that IMC-based detectors can meet 3GPP EVM specifications for QPSK, 16-QAM, and 64-QAM across both real-world (Argos) and synthetic (WINNER-II) wireless channels, achieving $7.2\times $ to $11.7\times $ better energy efficiency than digital detectors while incurring $\lt \mathrm {0.1~dB}$ penalty in receiver signal-to-noise ratio (RX SNR). We present extensive simulation results that provide insights into how parameters such as MIMO dimension, modulation scheme, precision of detection matrix, IMC bit-cell capacitance, IMC ADC precision, and ADC thermal noise impact the energy efficiency and accuracy of massive MIMO signal detection.