Open AccessAutomated Bitstream-Level Cost-Reliability Design-Space Exploration for SRAM-Based FPGAs
Author(s) -
Christian Fibich,
Martin Horauer,
Roman Obermaisser
Publication year - 2025
Publication title -
ieee transactions on computer-aided design of integrated circuits and systems
Language(s) - English
Resource type - Magazines
SCImago Journal Rank - 0.556
H-Index - 119
eISSN - 1937-4151
pISSN - 0278-0070
DOI - 10.1109/tcad.2025.3573225
Subject(s) - components, circuits, devices and systems , computing and processing
Triple Modular Redundancy (TMR) is a common approach to mitigate the effects of Single-Event Upsets (SEUs) in SRAM-based Field-Programmable Gate Arrays (FPGAs), where these faults may cause changes in the configuration of logic or interconnect resources. Partial TMR aims at balancing SEU mitigation with redundancy costs. This work introduces a Design-Space Exploration (DSE) approach that automatically generates and evaluates cost-reliability-optimized, Pareto-optimal partial TMR configurations of modules in a hierarchical design. The approach is evaluated using a proof-of-concept implementation for AMD’s 7 Series FPGAs and five case-study designs, including the NEORV32 RISC-V CPU. Multiple fitness assignment variants – based on static bitstream analysis, (statistical) fault injection results, and a combined approach –-are compared regarding effectiveness and runtime. Comparing the hypervolumes of the generated Pareto fronts of the final generation and a randomly generated starting generation, the approach improves cost-effectiveness of the generated TMR solutions by 17%–52%, delivering an attractive benefit-cost-ratio. The presented approach effectively generates a diverse set of TMR solutions across a wide cost-reliability range, allowing the designer to choose a variant that best fulfills the application’s, mission’s, or mission phase’s cost-reliability requirements.