Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Towards Power and EMSCA Resilience

Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at the VDD port. Although any digital implementation has two generic ports, namely clock and VDD, circuit-level countermeasures primarily focus on the VDD port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew, making it difficult for side-channel analysis. Due to this, minimum traces-to-disclosure (MTD) improves by 100× with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect (1800x) more than the multiplication of individual techniques (100x & 5x respectively) at the cost of 11% area overhead, <3% power overhead (measured), and <6% performance overhead (measured).