A 21.8–41.6-GHz Fractional-N Sub-Sampling PLL With Dividerless Unequal-REF-Delay Frequency Tracking

In this paper, a wideband millimeter-wave (mm-wave) fractional-N sub-sampling phase-locked loop (SSPLL) with low jitter and low power consumption is proposed. A dividerless unequal-REF-delay frequency-tracking-loop (URD-FTL) is introduced to ensure frequency locking over a wide mm-wave frequency range. By running the URD-FTL at the reference frequency instead of the oscillation frequency, the proposed design eliminates the need for high power millimeter-wave frequency dividers. The URD-FTL is disabled while phase locking without sacrificing the jitter performance. Besides, the mm-wave quad-mode oscillator and digital-to-time converter are integrated in the SSPLL to achieve a wideband fractional operation. The proposed fractional-N SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.17 mm. Measurements exhibit an output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100 MHz reference. The total power consumption is 11.6 to 14.8 mW, while the URD-FTL consumes only 680 μW. The SSPLL achieves a 135.4 to 167.5 fs jitter within the output frequency range, which leads to a FoMj from –246.7 to –243.9 dB. Meanwhile, the proposed SSPLL features a frequency locking acquisition.