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Integrating FPGA-Based Acceleration in Industrial Motion Control System
Author(s) -
Claudio Rubattu,
Antonio Ledda,
Francesco Ratto,
Chaitanya Jugade,
Dip Goswami,
Francesca Palumbo
Publication year - 2025
Publication title -
ieee open journal of the industrial electronics society
Language(s) - English
Resource type - Magazines
eISSN - 2644-1284
DOI - 10.1109/ojies.2025.3571218
Subject(s) - components, circuits, devices and systems , power, energy and industry applications
Manufacturing processes increasingly depend on advanced production machinery that must deliver high quality and large volumes. This applies to die-bonding machines as well that, especially at the time being after the years of shortage, need to meet very high standards of speed and accuracy. To achieve this, these devices are exploring the use of computer vision algorithms for automatic recognition of wafer positioning and die size. Nevertheless, these systems are typically managed by software-only solutions, which may fall short under stringent execution time requirements. A promising solution is the use of heterogeneous platforms, combining general-purpose processors with reconfigurable hardware. Such platforms offer the flexibility to handle both software tasks, which benefit from operating system support, and critical functions requiring hardware acceleration. This paper presents a closed-loop implementation of a vision-based multi-sensor control system for an industrial application. The implementation exploits the capabilities of System on Module (SoM) technologies to provide flexible I/O and software execution coupled with computing acceleration for the vision algorithm on the reconfigurable Field Programmable Gate Array (FPGA) fabric. The FPGA coprocessor has been designed leveraging the High-Level Synthesis (HLS) technology and optimized on a dataset of 10k realistic images to meet the industrial use case's performance, communication, and accuracy requirements. Moreover, the resulting accelerator performance and resource utilization demonstrate the possibility of reaching state-of-the-art metrics of handwritten hardware designs while allowing for higher abstraction and productivity of the design process.

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