Comprehensive device to system co-design for SOT-MRAM at the 7nm node

This work presents a comprehensive spin-orbit torque (SOT) based random access memory (MRAM) design at the 7nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device-level, we show the trade-offs among the write current, error rate, and time, based on mircomagnetic simulations. Based on ASAP7 PDK design rules, we create the bit-cell and peripheral layouts for SOT-MRAM and design the entire array. In addition, we quantify various array-level trade-offs using full array SPICE circuit simulations based on layout-extracted parasitic netlists. This is then used to design the entire SOT-MRAM system along with a memory controller. Based on place and route, we evaluate the system-level PPA for various memory capacities, demonstrating bit-densities up to 14.8 Mb/mm 2 and read bandwidths up to 2.98 GB/s. Our results show that increasing the memory size from 1 Mb to 16 Mb results in a performance degradation of ∼33-38% due to the impact of interconnect delay. As the results show that the performance of SOT-MRAM is limited by the interconnect delay, it is critical to co-optimize the device and interconnect technology to make SOT-MRAM a viable option at the advanced technology nodes. In addition, material discovery for field-free perpendicular magnetization switching in SOT devices based on out-of-plane spin torque is necessary to achieve SRAM level write energies.