1.58b FeFET-based Ternary Neural Networks: Achieving Robust Compute-in-Memory with Weight-Input Transformations
Author(s) -
Imtiaz Ahmed,
Akul Malhotra,
Revanth Koduru,
Sumeet Kumar Gupta
Publication year - 2025
Publication title -
ieee journal on exploratory solid-state computational devices and circuits
Language(s) - English
Resource type - Magazines
SCImago Journal Rank - 0.545
H-Index - 16
eISSN - 2329-9231
DOI - 10.1109/jxcdc.2025.3621160
Subject(s) - components, circuits, devices and systems , computing and processing
Ternary weight neural networks (TWNs), with weights quantized to 3 states (-1, 0, and 1), have emerged as promising solutions for resource-constrained edge artificial intelligence (AI) platforms due to their high energy efficiency with acceptable inference accuracy. Further energy savings can be achieved with TWN accelerators utilizing techniques such as computing-in-memory (CiM) and scalable technologies such as ferroelectric transistors (FeFETs). Although the standard 1T-FeFET CiM design offers high density with their compactness and multilevel storage, their CiM performance in deeply scaled technology is prone to hardware non-idealities. This requires design modifications such as 2T-FeFET bitcells, offering high CiM robustness due to their differential nature at the cost of area. In this work, we conduct a design space exploration of FeFET-based TWN-CiM solutions. By utilizing FeFETs storing 1-bit (2-levels) and 1.58 (log23) bits (3-levels), we design three flavors of ternary CiM arrays: (i) 1T design based on 1.58b FeFET (1T), (ii) 2T differential design (2T-diff) and (iii) 2T pull-up/pull-down (2T-PUPD) design. Additionally, to increase the computational robustness of 1T design, we propose static weight-transformation (WT) and static-weight & dynamic-input transformation (WIT). We then comparatively evaluate the inference accuracy and energy-area trade-offs of the these designs. For this, we use phase-field models to capture the multi-domain physics and a rigorous inference simulator accounting for hardware non-idealities such as array parasitics. Our analysis for ResNet18 trained on CIFAR100 dataset shows that, 1.58b 1T-bitcell with WT and WIT techniques yield significant improvement in inference accuracy (73.61%) compared to the standard 1T design (i.e. without WIT). This accuracy is comparable to the 2T-diff design (76.4%), with 1.98× and 1.91× reduction in overall area and CiM energy, respectively.
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