Non-Volatile ReRAM based compact event triggered counters

With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increases exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilises a combination of CMOS circuits and memristors (ReRAM), thereby reducing the number of transistors and finding applications in Artificial intelligence (AI) circuits. Two types of a 16-bit digital counter has been designed, one of which is a classically designed D-Flip-Flop using memristors as logic gates, followed by an improved design that significantly reduces the number of components. The results of the design and simulation of 16-bit digital counters are presented with a expected counter function. The simulation is based on experimentally measured parameters of memristors and a functional model. Furthermore, in-depth analyses with respect to practical memristor results are discussed, including variations in Set/Reset potential, endurance and retention characteristics, post-layout effects on the proposed circuit, and the associated power consumption.