A Hardware Implementation of Spaceborne SAR BP Algorithm Based on Precise Region Focusing and Hardware-Software Collaboration

Onboard imaging of Spaceborne Synthetic Aperture Radar (SAR) is a key technology in the field of high-timeliness remote sensing applications. It adopts the hardware platform deployed on the satellite to convert the SAR radar echoes into visual images. Combined with image detection and recognition, it can rapidly downlink and distribute the effective information. At present, high-resolution and wide-swath imaging is the development trend of spaceborne SAR imaging. The Back Projection (BP) algorithm is an excellent high-resolution imaging algorithm for spaceborne SAR, but it demands large storage resources and involves heavy computations. Given the limited resources of the satellite's hardware platform, the traditional hardware implementation of the algorithm can hardly support large-scale scenes imaging. Even if it can, the imaging time is extremely long. This paper proposes an improved Cartesian Factorized Back Projection (CFBP) algorithm based on precise region focusing. By dividing the imaging sub-regions and using a stepped data reading method, the demand for storage can be significantly reduced. Moreover, a software-hardware collaboration method based on scheduling acceleration is put forward. Through constructing an ultra-long projection pipeline, the continuity and speed of the algorithm execution can be enhanced. According to the proposed method, a Projection Intellectual Property (IP) and a complete imaging system are constructed using the Xilinx VU9P Field Programmable Gate Array (FPGA) board. Experimental results show that the Projection IP can save up to 40.78% - 85.09% of Random Access Memory Blocks (BRAM), and the projection calculation time can be reduced by up to 54.54%. The complete imaging system can process the improved CFBP projection algorithm for images of sizes 32 K × 32 K, 16 K × 16 K, and 8 K × 8 K within 2308.11 seconds, 598.07 seconds, and 167.81 seconds, respectively. Compared with other FPGA-related research, it supports large-size scene imaging and demonstrates excellent performance in terms of effective computing power( $P_{p}$ ) and storage resource utilization( $P_{m}$ ).