Substrate Current Enhances HCI Lifetime in STI-Based LDMOS

There is an increasing demand for LDMOS with low RON, high IDSAT, and longer HCI lifetime offered by standard CMOS technology. We achieved these demands without introducing additional processes or altering the LDMOS design. Increasing the dose and energy in the high-energy Well implant reduced drain resistance and prevented doping in the channel caused by it. As a result, the RON and IDSAT of LDMOS were improved while maintaining the same CMOS characteristics. There was a side effect of increasing substrate current, which is widely known to degrade HCI lifetime. However, the test results showed it was 10 times longer than the control. To verify this unexpected result, we evaluated the IDSAT degradation in samples fabricated with various implant conditions. The results showed that it was negatively correlated with substrate current and decreased as the substrate current increased. The mechanism is that many electRONs generated by impact ionization are trapped in the STI oxide in the drain as they travel to the drain terminal. These electRONs create a depletion layer in the adjacent drain, increasing the drain resistance. Increasing the dose in the drain enhances the number of trapped electRONs along with the substrate current, degrading RON. However, simultaneously, it also increases doping and suppresses RON degradation. As a result, the HCI lifetime was enhanced despite the larger substrate current.