Front-Side NMOS Connection as the Preferred Scheme: Quantifying the ~10× Resistance Limit of NMOS-Backside in DBC 3DSFET SRAM | Zendy

Yunho Shin | Zendy; Duckseoung Kang | Zendy; Daewoong Kwon | Zendy; Ilho Myeong | Zendy

Open Access

Front-Side NMOS Connection as the Preferred Scheme: Quantifying the ~10× Resistance Limit of NMOS-Backside in DBC 3DSFET SRAM

Author(s) -

Yunho Shin,

Duckseoung Kang,

Daewoong Kwon,

Ilho Myeong

Publication year - 2026

Publication title -

ieee access

Language(s) - English

Resource type - Magazines

SCImago Journal Rank - 0.587

H-Index - 127

eISSN - 2169-3536

DOI - 10.1109/access.2026.3662366

Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation

In 3-Dimensional Stacked FET (3DSFET) technology beyond the 1 nm node, direct backside contact (DBC) has emerged as an effective approach to continue scaling of both logic and SRAM bit cells. Two NMOS connection strategies under DBC integration—backside routing and front-side routing—are analyzed. The hybrid configuration, with PMOS using DBC and NMOS using front-side contact, achieves ~30% SRAM bit cell area reduction and performance gains of 7.2% in PD/PG on-current, 4.7% in IREAD, and 7.2% in Gamma. In contrast, backside NMOS routing increases area and resistance, but reliable operation is preserved as long as resistance growth is limited to ~10×, establishing a practical margin for DBC adoption in future high-density SRAM.

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