Double-Node-Upset Fully-Tolerant/Recoverable and Triple-Node-Upset Partially-Tolerant Self-Recoverable Latch Design for Aerospace Applications | Zendy

Urmila Saha | Zendy; Bayartulga Ishdorj | Zendy; Jaeyong Jang | Zendy; Taehui Na | Zendy

Open Access

Double-Node-Upset Fully-Tolerant/Recoverable and Triple-Node-Upset Partially-Tolerant Self-Recoverable Latch Design for Aerospace Applications

Author(s) -

Urmila Saha,

Bayartulga Ishdorj,

Jaeyong Jang,

Taehui Na

Publication year - 2025

Publication title -

ieee access

Language(s) - English

Resource type - Magazines

SCImago Journal Rank - 0.587

H-Index - 127

eISSN - 2169-3536

DOI - 10.1109/access.2025.3631628

Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation

Due to the continuous scaling down of transistor size in integrated circuits, sensitive nodes are becoming increasingly vulnerable to node upset, especially in aerospace, because of their high radiation environment. This paper presents a low-cost double-node-upset (DNU) fully-tolerant and triple-node-upset (TNU) partially-tolerant self-recoverable latch (DFTPRL) design utilizing a high transmission path and clock-gating technique. The proposed latch design provides high stability and rapid response against DNU, while also maximizing TNU tolerance by incorporating a maximum number of logic stages between nodes for self-recovery. Post-layout HSPICE simulation results using 28 nm model parameters clearly show the reliability of the proposed DFTPRL.

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