Close-to-Functional Simulation-Model-Based Tests for Single-Cycle Interconnect Faults

Chiplet-based designs consist of large numbers of logic blocks (chiplets) that are connected by a large number of interconnects. The interconnects require thorough testing to ensure the correct operation of the design. Standard isolation logic allows the logic blocks and interconnects to be tested separately. During functional operation, the logic blocks drive the interconnects, and defects that are only exhibited during functional operation may not be detected when the logic blocks and interconnects are tested in isolation. A possible solution, before resorting to functional tests, is to ensure that a test set for a logic block also tests the interconnects that the logic block drives without using the isolation logic between them. This article studies this issue for the first time in the scenario where only a compressed test set and a simulation model are available for the logic block, and its internal description is not available. The article describes a test generation procedure that uses the compressed test set for the logic block and its simulation model to generate a test set that targets the interconnects. Experimental results for benchmark circuits in an academic simulation environment demonstrate the effectiveness of the procedure in using a compressed stuck-at test set for a logic block to generate tests for an exhaustive single-cycle interconnect fault model.