SOP network optimization methods aimed at reducing switching activity

One of the leading concepts in the development of digital circuits is to ensure the highest possible energy efficiency of implemented logic structures. In addition to power reduction through technology, there are also techniques that allow for algorithmic reduction of power consumption. This power is called dynamic power and for combinational circuits strongly depends on a parameter called switching activity. It turns out that switching activity can be limited algorithmically in the process of logic synthesis. The article presents considerations for logic structures in the form of a Sum Of Products (SOP), with a specified (constant) number of products. The choice of the method of mapping logic functions in the SOP structure is crucial. One of the most popular methods is the classical implementation leading to the creation of a logic network of a cascade nature. This method, despite many disadvantages such as poor efficiency in terms of the use of logical resources (and consequently increased power consumption), has undoubted advantages. The main advantages include: high reliability, simple synthesis algorithms and often good results in terms of dynamic properties. The authors propose two techniques for limiting switching activity in SOP structures mapped by the classical method: implicant displacement and optimization of routing connections between SOP blocks. Naturally, both methods can be implemented in parallel. The proposed algorithms have been tested on a popular set of benchmarks. The experimental results have confirmed the effectiveness of the methods proposed in the article.