Novel Approximate Floating-point Adder with runtime tunable precision

This paper proposes a novel low-power approximate floating-point adder with runtime configurable precision. The design combines skipping addition, triggered when the exponent difference exceeds a programmable threshold, with tunable mantissa rounding to reduce switching activity. We present a comprehensive analysis aimed at identifying the most appropriate combination of skipping and rounding thresholds that enables the best balance between precision and power consumption. The thresholds are controlled by an accuracy control signal, which can be modified at runtime to achieve the desired power-precision trade-off. A detailed comparison with state-of-the-art designs was carried out in FP32 and FP16 formats, considering implementations in 28nm technology. The proposed approximate floating-point adder outperforms existing approaches in the power-precision trade-off, while also offering the unique advantage of runtime configurability. This flexibility comes at the cost of a moderate area increase, mainly due to the additional control logic for configurability. Power savings over the exact adder range from 45% to 60% in FP32 and from 20% to 53% in FP16, with the mean relative error distance tunable between 1.34×10 −8 and 6.34×10 −6 in the FP32 and from 5.07×10 −4 to 1.78×10 −2 in FP16. The effectiveness of our configurable adder is validated in three practical applications: JPEG image compression, convolution-based image processing (filtering and edge detection), and time sequence prediction using a Long Short-Term Memory recurrent neural network. In all the tests the proposed adder consistently delivered string performance, confirming the practical relevance of the proposed technique.