Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration

Although many annealing algorithms and processors have been proposed to solve combinatorial optimization (CO) problems, their comparative advantages under varying problem characteristics remain largely unexplored. This limitation arises from the lack of a unified platform capable of executing multiple annealing algorithms under consistent and fair conditions. To address this issue, we propose a generalized parallel annealing algorithm, Ratio-controlled Parallel Annealing (RPA), and present Amorphica, a custom-designed ASIC that supports four distinct annealing policies: Simulated Annealing (SA), Digital Annealer’s algorithm (DA), Stochastic Cellular Automata Annealing (SCA), and the proposed RPA. Amorphica features a micro-architecture that supports programmable annealing policies and scalable multi-chip operation with full spin connectivity. Amorphica has been fabricated in 40nm CMOS technology with an 8Mb on-chip SRAM. It operates at 336–369MHz under a 1.1V supply, and consumes an average of 44–95mW at 0.8V, depending on the annealing policy. Through extensive benchmark evaluations against a 250W-class GPU, Amorphica demonstrates competitive solution quality, energy efficiency, and execution speed. Notably, it achieves up to 80.7× speedup while consuming only about 0.2% of the power when solving dense Maxcut instances with controlled edge weight distributions. To the best of our knowledge, Amorphica is the first annealing processor to integrate multi-policy control, full connectivity, and multi-chip scalability into a single hardware platform.