Resource-Efficient FPGA Implementation of a Two-Layer Perceptron for Real-Time Medical Image Classification Using a Hybrid VGG-Attention Framework

The success of deep neural networks in image processing is dependent mainly on their architectural design, especially regarding the feature extraction component and the arrangement of neurons in the fully connected (FC) layers of the classifier. Implementing the classifier on an embedded computing platform, such as a Field Programmable Gate Array (FPGA), enables direct evaluation on the hardware level. Research indicates that specific parameters within the FC layers can lead to overfitting; hence, a hybrid VGG framework has been proposed. This framework improves feature extraction through a refined subtle-local feature extraction pooling technique, followed by attention mechanisms that preserve spatial details more effectively. Subsequently, a Two-Layer Perceptron (TLP) classifier with a minimal number of neurons is utilized. For real-time applications, the TLP is implemented on an FPGA using low-precision fixed-point quantization, optimizing resource utilization and reducing latency without compromising accuracy. Through a comprehensive exploration of model architecture, the proposed TLP achieves a notable classification accuracy of 96.42% on an unseen dataset, utilizing lightweight resources: 14.54% LUT, 2.89% FF, and 0.71% Block RAM (BRAM) on the ZYNQ7000-XC7Z020 with OLED, and 35.76% LUT, 7.10% FF, and 1.00% BRAM on the Artix-7 XC7A35T with a seven-segment display. This design approach enables efficient real-time inference in medical image classification tasks on an edge computing environment, ensuring robustness and practical applicability.